The present invention relates to computer systems, and particularly to computer systems using large numbers of dynamic random access memories ("DRAMs").
DRAMs are the lowest-cost type of semiconductor memory. DRAMs are therefore used in a very wide variety of computer systems, and in other electronic systems as well.
However, DRAMs require refreshing. Information is represented by the presence or absence of electric charge in each DRAM cell. For example, a "1" might be written into a DRAM cell by storing a packet of charge in the cell, and a "0" by not storing a packet of charge. However, these packets of charge are very small, and they rapidly leak away. Depending on various factors, the data stored in a DRAM cell may become unreadable within less than 1/10th of a second after it has been written.
Therefore, to maintain stable storage of data, it is necessary to periodically read out each of the cells in the chip, amplify the data signal from the cell, and write the amplified data signal back into the cell. This function is well known to those skilled in the art of computer memory system design. Many chips are available to perform "memory management" functions, such as determining when another refresh cycle must be initiated for the DRAM chips in a memory bank.
Unless a DRAM receives refresh signals and power, the stored data will be lost. Therefore, the data in a conventional memory bank composed of DRAMs will disappear whenever a significant power interruption occurs. It would be highly desirable to avoid this vulnerability to power interruption, but no commercially feasible way to accomplish this has yet been presented.
SRAMs (static random access memories), like DRAMs, are volatile. That is, SRAMs too will lose their data as soon as power is interrupted. However, a relatively recent development has permitted systems using SRAMs to achieve nonvolatility. The SmartSocket (TM), marketed by Dallas Semiconductor Corporation, is a socket which includes a small lithium battery and a controller circuit, so that a CMOS SRAM can be maintained in standby status when the system power supply fails. This product has proven to be extremely useful to system designers.
DRAMs, unlike SRAMs, do not have a very low power standby mode, and do require refresh operations. These factors make it more difficult to implement battery backup for DRAM memory. Another difficulty is that DRAMs tend to be more sensitive to power supply voltage fluctuations than SRAMs are.
The present invention enables memory subsystems where standard commercial DRAMs can be used, but wherein the data in the DRAMs is nonvolatile, i.e. is safeguarded against power failure. The present application sets forth a number of innovative teachings which permit DRAM nonvolatility to be achieved. Some significant ones of these teachings are as follows. Of course, most of these innovative teachings could be applied independently.
1. The DRAM chips used are preferably those where row addresses for refresh need not be externally supplied. Thus, for example, chips such as the first generation 256K DRAMs would not be used. Instead, standard one megabit chips, or later-generation 256K chips could be used, where refresh is triggered (e.g.) by a CAS-before-RAS, and the chip has an internal counter which points to the next row for refresh.
2. In the presently preferred embodiment, one controller chip is used with each bank of nine DRAMs, to provide nonvolatility. This approximate ratio of controller chips to memory chips turns out to be particularly advantageous. However, less preferably, more or fewer memory chips per controller could be used.
3. When the system power has been interrupted, power is supplied from a battery whose operating voltage is higher than the highest normal value of the system power supply.
4. On power failure, a burst mode refresh cycle is preferably initiated immediately. (A "burst mode" refresh cycle is one where all of the rows are refreshed one after another, as rapidly as possible.)
5. A bandgap-regulated reference voltage generator is used to accurately regulate the standby power supply voltage supplied to the DRAM chips. This voltage is set near the high end of the permissible range. The regulator has significant hysteresis. A trimmable resistor network permits high absolute accuracy. The use of a high battery voltage and precise regulation also means that a wide range of battery voltages can be tolerated. A relatively large capacitor is preferably tied to the regulated power supply output of each controller chip. This permits an effective output impedance which is lower than that of the battery.
6. Both high-voltage and low-voltage NMOS and PMOS transistors are used. This permits a higher voltage to be used on the battery, while still providing low-impedance switches. (Low-impedance switches are needed to avoid clock skew in the RAS* and CAS* signals, which are received from the system and passed on to the DRAM bank during normal operation. These RAS* and CAS* signals may have to drive as much as 300 picoFarads of capacitive load in a bank of nine DRAMs).
7. A battery usage counter is preferably included in the controller chip. Thus, a system status output pin can be used to indicate that a battery is nearing the end of its lifetime (or has failed catastrophically). In addition, the battery lifetime counter data can be read out or rewritten by the system.
8. The standby functionality is selectable. Therefore, the system may select some memory banks to be nonvolatile, and command others not to be nonvolatile. This means that the power in the standby batteries can be conserved during storage and shipping, or whenever the system determines that the DRAM data does not need to be protected.
9. When power is restored, the system must request the control chip to hand back control. This assures a clean hand-off on power up, even if the system power supply is momentarily interrupted during the power-up transition. As soon as the supply voltage has been restored, a continuous series of refresh commands is initiated. Thus, when the system resumes control, the DRAM chips will already be maximally refreshed.
10. To generate the RAS* and CAS* signals with appropriate timing during battery backup operation, an oscillator is used which is voltage and temperature insensitive.
11. Floating well devices are used in the local power supply regulator, to assure that the devices are insensitive to the sign of voltage difference between the system power supply and the standby power supply.
The present invention provides numerous advantages, including at least the following:
Nonvolatile memory modules can readily constructed using common commercial DRAM chips. This provides very low cost nonvolatile memory modules of large capacity.
Moreover, the nonvolatile memory modules thus supplied can be written to and read from extremely rapidly. (One of the problems with using EPROM or EEPROM memory is that the write speeds are extremely slow.)
The nonvolatile memory modules provided by the present invention are highly architecturally compatible with many existing DRAM-based archittectures. Thus, with many system architectures, nonvolatile memory modules according to the present invention can be directly plugged in the place of a conventional DRAM memory module. By contrast, conventional nonvolatile memory technologies require different architectural environments than DRAM technology. Thus, this feature of full architectural compatibility can be extremely important to system designers.
Computer, consumer, or telecommunication systems built using such nonvolatized DRAM memory modules have substantial advantages over comparable systems using conventional DRAM modules. For example, data loss due to common occurrences such as a user kicking a plug is eliminated. Moreover, data loss due to powerline spikes or dropouts is also eliminated. Optionally, a system may use not only nonvolatile DRAM modules as described herein, but also battery-backed power failure protection for all microprocessors and all other types of memory present in the system. This means that a system can be provided which is fully nonvolatized against power interruptions.
The various innovations described also provide a nonvolatile DRAM system which is as insensitive as possible to the phase of DRAM refresh cycles. That is, in systems built according to the innovative teachings disclosures herein, it does not matter whether a power failure occurs just after a particular memory bank has been refreshed, or just before that memory bank was due to be refreshed again.
The presently preferred embodiment also provides substantial advantages of reduced temperature dependence. The behavior of integrated circuits generally tends to be somewhat temperature-dependent. For example, normal logic elements, in a CMOS integrated circuit, will normally run somewhat slower at higher temperatures. In some contexts, this normal temperature-dependence can be very undesirable.
U.S. Pat. No. 4,406,013 has suggested a DRAM refresh generator which provides more frequent refreshing at higher temperatures. However, relatively complex circuitry is normally needed to accomplish this.
The present invention has the advantage of providing a very simple circuit which avoids increased delay at higher temperature.